3Plus1 Technology Describes Architectural Strategies for Ultra Low Power Wireless Processors at DAC 2005

Prof. Jan Rabaey, UCB, Leads Wireless Platforms Panel Session, 'GOP's for Cents for Milliwatts'

Panel Session Questions the Validity of Conventional Architectures for Efficient Wireless Platform Implementation

SARATOGA, Calif., June 15 /PRNewswire/ -- 3Plus1 Technology Inc., today describes its groundbreaking approach to next generation wireless implementation platforms at 2005 Design Automation Conference (DAC) in Anaheim, CA.
 

Professor Jan Rabaey, Berkeley Wireless Research Laboratory, University of California at Berkeley, moderates the five member panel and based on the observation that "data communication has taken over from voice as the main force behind the growth wireless revenues" and hence "the opportunities offered by ubiquitous connectivity are tremendous, leading to revolutionary changes in the way that computer, communication and consumer systems operate and interact."
 

"We are honored to join this debate and give a comparative insight into next generation architectures for fully software programmable wireless platforms that address the new market opportunities," said Allan Cox, 3Plus1 Technology's President and CEO, "the notion of concurrent voice, video and data application scenarios that can be flexibly run in a single processor is now a reality, together with an acceptable power and price point for next generation mobile wireless systems."
 

3Plus1 describes the modem and codec based applications that are required in next generation systems and the large increase in processing "GOP's" that are needed for running these in real time. Market driven metrics are then described for silicon area and processor core power for these scenarios.
 

Based on two years of research and development effort, 3Plus1 describes the five vectors of power, price (silicon area), performance, programming ease and programming flexibility and maps competing architectural approaches, such that true relative efficiencies can be seen easily.
 

Finally, the company describes its basic architectural approach that results in a compelling "GOP's per milliwatt per cent" and details the hierarchical compilation strategy that enables not only a flexible programming model but also one which is highly user friendly.
 

Formed in 2003, 3Plus1 Technology has created an architecture specifically designed for low-power, concurrent execution of specific modems and codecs, including WiFi, WiMax, Bluetooth, UWB, GSM/GPRS/EDGE, WCDMA, GPS, MPEG 2/4, H.263/4, MP3, AAC, and JPEG/2000 in various combinations. This has been accomplished in a sub-100mw processor core when implemented in a standard 130nm low-power CMOS process.
 

Financed by its founders since its inception, with additional income from sales of its first tools and services, the company is addressing the needs of the 600-million-plus handset, mobile media player, camera and PDA market. 3Plus1 has assembled a group of world-class technologists, including leading academics in their fields, addressing the problems of real-time voice, video and data processing -- at ultra low power levels and minimum silicon die size -- from the fundamental software and hardware architectural perspectives.
 

The CoolProcessor technology has been developed in record time, based on an internally developed, automated methodology, capable of generating RTL, simulation, analysis and verification tools automatically from a high-level design database.
 

The CoolProcessor family comprises six members, all upwardly code compatible with a single programming model. Development of software applications follows a standard DSP tool flow and the company is currently delivering its initial applications-development software and modeling tools to early evaluation partners.
 

Source: 3Plus1 Technology Inc.

CONTACT: Allan Cox, President and CEO of 3Plus1 Technology, Inc.,
+1-408-370-3104
 

Web site: http://www.3p1t.com/